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7.3.2
CWProt
This bit is set to ‘ 1 ’ when the bit RWProt changes state. This bit can also be written by the host.
7.3.3
Rready
This bit is used to determine the internal state of the Ready signal. In I/O mode it is used as an interrupt request.
When written, this bit acts as a mask (Mready) for writing the corresponding bit Cready.
7.3.4
Wprot
This bit is always ‘0’ since the CompactFlash TM Memory Card does not have a Write Protect switch. When written,
this bit acts as a mask for writing the corresponding CWProt bit.
7.3.5
Mready
This bit acts as a mask for writing the corresponding Cready bit.
7.3.6
MWProt
This bit when written acts as a mask for writing the corresponding CWProt bit.
Table 36: Pin Replacement Register (default value: 0Ch)
Operation
Read
Write
D7
0
0
D6
0
0
D5
Cready
Cready
D4
CWProt
CWProt
D3
1
0
D2
1
0
D1
Rready
Rready
D0
Wprot
MWProt
Table 37: Pin Replacement Changed Bit/Mask Bit Values
Initi al Value of ‘C’ Status
Written by Host
‘C’ Bit ‘M’ Bit
Final ‘C’ Bit
Comments
0
1
X
X
X
X
0
1
0
0
1
1
0
1
0
1
Unchanged
Unchanged
Cleared by Host
Set by Host
7.4 Attribute Memory Function
Attribute memory is a space where identification and configuration information are stored. Only 8 bit wide
accesses at even addresses can be performed in this area. The Card configuration registers are also located in the
Attribute Memory area, at base address 200h. Attribute memory is not accessible in True IDE mode of operation.
For the Attribute Memory Read function, signals – REG and – OE must be active and – WE inactive during the cycle.
As in the Main Memory Read functions, the signals – CE1 and – CE2 control the even and odd Byte address, but only
the even Byte data is valid during the Attribute Memory access. Refer to Table 38 for signal states and bus validity.
Table 38: Attribute Memor y Function
Function Mode
Standby
Read Byte Access CIS (8 bits)
Write Byte Access CIS (8 bits)
Invalid
Read Byte Access
Configuration (8 bits)
Write Byte Access
Configuration (8 bits)
Read Byte Access
Configuration CF+ (8 bits)
Read Word Access CIS (16
bits)
Write Word Access CIS (16
bits) Invalid
Read Word Access
Configuration (16 bits)
Write Word Access
Configuration (16 bits)
-REG
X
L
L
L
L
L
L
L
L
L
-CE2 (1)
H
H
H
H
H
H
L
L
L
L
-CE1 (1)
H
L
L
L
L
L
L
L
L
L
A10
X
L
L
L
L
X
L
L
L
L
A9
X
L
L
H
H
X
L
L
H
H
A0
X
L
L
L
L
L
L*
L*
L*
L*
-OE (1)
X
L
H
L
H
L
L
H
L
H
-WE (1)
X
H
L
H
L
H
H
L
H
L
D15 to D8
High-Z
High-Z
Don’t Care
High-Z
Don’t Care
High-Z
Not Valid
Don’t Care
Not Valid
Don’t Care
D7 to D0
High-Z
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
1
The – CE signal or both the – OE signal and the – WE signal must be de-asserted between consecutive cycle operations.
* Address A0 must be low for all word accesses.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
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